As non-volatile semiconductor memory devices, there an EPROM which stores "0" data or "1" data into memory cell by injecting or not injecting electrons into a floating gate. The threshold voltage of a data-written memory cell wherein the electrons are injected is higher than that of a data-erased memory cell which is erased by ultraviolet light. Namely, the data "0" or "1" stored in a memory cell is read by checking whether a current flows through the memory cell when the drain of the memory cell is biased to a predetermined potential. An EPROM of CMOS structure according to the background art is shown in FIG. 1. In FIG. 1, a memory cell array MCA.sub.1 has n.times.l.times.m memory cells. Each memory cell MC.sub.ijk (i=1, . . . , n, j=1, . . . , l, k=1, . . . , m) has a drain connected to a bit line BL.sub.ik, a source connected to a ground line, and a control gate connected to a word line WL.sub.j. Each of n.times.m bit lines BL.sub.ik is connected via column gate transistors h.sub.ik and g.sub.i to a node N1 of a bias circuit 10. One of word lines WL.sub.j (j=1, . . . , l) corresponding to a row address is selectively driven by a row decoder DE.sub.R. A pair of column gate transistors h.sub.ik and g.sub.i corresponding to a column address is seleCtively driven by a column decoder DE.sub.C.
Accordingly, a memory cell MC.sub.111 for example is accessed by selecting the column gate transistors g.sub.1 and h.sub.11 and the word line WL.sub.1.
FIG. 1A shows a device having a memory cell array MCA.sub.2 which has no column gate transistor g.sub.i. The other arrangement is the same as that shown in FIG. 1.
A bias circuit 10 has inverters INV1 and INV2, N-channel transistors T4 and T8, and a P-channel load transistor T9. This circuit 10 supplies a bias potential to the bit line BL.sub.ik to which the drain electrode of a selected memory cell MC.sub.ijk is connected. The potential at the output terminal (node N2) of the bias circuit 10 changes in accordance with the data stored in a selected memory cell MC.sub.ijk.
When the "0" data is stored in the selected memory cell, the potential of the node N2 is a high level. On the other hand, when the "1" data is stored in the selected memory cell, the potential of the node N2 is a low level. It is possible to achieve a fast data read from a memory cell MC.sub.ij by quickly charging the bit line BL.sub.ik from 0 V to a first predetermined voltage. To quickly charge the bit line bl.sub.ik, the transistor T4 is connected between the node N1 and the power source (whose voltage value is Vcc). The first predetermined voltage is equal to the voltage of the bit line BL.sub.ik connected to a selected memory cell MC.sub.ijk when the memory cell MC.sub.ijk is data-erased memory cell.
The gate electrode of the transistor T4 is connected to the output terminal of the inverter INV1 having P-channel transistors T1 and T2 and an N-channel transistor T3 whose threshold voltage is near 0 V. A chip control signal CE* is applied to the gate electrode of the transistor T1. This chip control signal CE* is 0 V when the semiconductor memory chip is selected, and is the power source voltage Vcc (=5 V) when not selected. The gate electrodes of the transistors T2 and T3 are connected to the node N1. The output of the inverter INV1 is set such that the transistor T4 is made conductive when the potential at the node N1 is equal to or lower than the first predetermined voltage, and made non-conductive when it exceeds the first predetermined voltage.
The node N1 is coupled via the N-channel transistor T8 to node N2. The gate electrode of the transistor T8 is connected to the output terminal of the inverter INV2 having P-channel transistors T5 and T6 and an N-channel transistor T7 whose threshold voltage is near 0 V. Similarly to the transistor T1, the chip control signal CE* is applied to the gate of the transistor T5. The gate electrodes of the transistors T6 and T7 are connected to the node N1. The output of the inverter INV2 is set such that the transistor T8 is made conductive when the potential at the node N1 is equal to or lower than a second predetermined value. The second predetermined voltage is higher than the first predetermined voltage (e.g., by about 0.1 V) and is equal to the voltage of the bit line BL.sub.ij connected to a selected memory cell MC.sub.ijk when the memory cell MC.sub.ijk is data-written memory cell. The P-channel load transistor T9 is connected between the node N2 and the power source, the gate electrode of which is connected to the node N2.
The potential at the output terminal (node N2) of the bias circuit 10 takes a low level V.sub.L (e.g., about 1 V) when a selected memory cell MC.sub.ijk is in a data-erased state, and takes a high level V.sub.H (=Vcc-.vertline.V.sub.THP .vertline.) in a data-written state. Here, V.sub.THP represents the threshold voltage Of the p-channel transistor T9. The potential at the node N2 is compared with the reference potential at the node N4 in a reference potential generating circuit 60 to be described later. The comparison results are generally outputted via an output buffer circuit (not shown) to the external circuit as the read-out data.
The reference potential generating circuit 60 has a reference cell RMC of the same transistor size as that of a memory cell MC.sub.ijk, N-channel transistors T11 and T12, and a bias circuit 65. The reference Cell RMC has a gate electrode connected to the power source, a source electrode connected to the ground line, and a drain electrode connected to the bias circuit 65 via the transistors T11 and T12. The transistors T11 and T12 are constructed of the same transistor size as that of the column gate transistors h.sub.ik and g.sub.i. The bias circuit 65 is constructed the same as the bias circuit 10, except that a P-channel load transistor T10 has a smaller conducting resistance than the transistor T9. Inverters and transistors corresponding to those in the bias circuit 10 are represented by using identical reference symbols. Node N3 in the bias circuit 65 corresponds to the node N1 in the bias circuit 10, and node N4 in the bias circuit 65 corresponds to the node N2 in the bias circuit 65. The potential at the output terminal (node N4) of the bias circuit 65, i.e., the reference potential V.sub.R, is set to have an intermediate potential between the high level V.sub.H and low level V.sub.L at the output terminal (node N2) of the bias circuit 10. The difference of the potential at the node N2 and the reference potential V.sub.R are sensed at a current mirror type differential amplifier 30 having P-channel transistors T13, T14 and T15, and N-channel transistors T16 and T17. If the potential at the node N2 is higher than the potential (reference potential V.sub.R) at the node N4, the output D* of the differential amplifier 30 has a low potential, and if the former is lower than the latter, the output D* becomes a high potential. The output D* is delivered to an external circuit via an output buffer circuit.
The gate electrode of the transistor T13 of the differential amplifier 30 is supplied with the chip control signal CE*.
With the semiconductor memory device constructed as above, according to the background art, there is a problem that an erroneous operation is likely to occur when the power source voltage Vcc fluctuates, because the conducting resistance of the load transistor T9 of the bias circuit 10 is different from that of the load transistor T10 of the bias circuit 65. This will be described with reference to FIGS. 2 and 3. FIG. 2 shows the current flowing through the load transistors T9 and T10 when the drain voltage of each load transistor changes. In FIG. 2, it is assumed that the current I cell flows through a memory cell in the data-erased state. When a selected memory cell is the data-erased memory cell, the potential at the node N2 becomes a low level V.sub.L (refer to line l.sub.1) and the potential (reference potential) at the node N4 becomes V.sub.R (refer to line l.sub.3). When a selected memory cell is the data-written memory cell, the potential at the node N2 is charged up to a high level VH.sub.H, and the current flowing through the transistor T9 becomes 0 .mu.A (refer to line L.sub.1). If a selected memory cell is the data-written memory cell, the node N1 and the selected bit line are charged to the second predetermined potential, and the node N2 is charged up to the high level V.sub.H by the load transistor T9.
In this condition, the output potential of the inverter INV2 is the low potential which is higher than the second predetermined potential of the node N1 by the threshold voltage of the transistor T8. If the power source voltage changes in the positive direction relative to the ground potential because of noise components on the power source, the output potential of the inverter INV2 also changes in the positive direction above the predetermined low potential. Therefore, if noise is generated on the power source, the transistor T8 is made conductive also and the node N1 and the bit line are charged up above the second predetermined potential. It is assumed that a current I.sub.1 .mu.A flows from the node N2 to the node N1 via the transistor T8 when the noise is generated on the power source.
Since the bias circuit 65 of the reference potential generating circuit 60 has the same circuit structure as the bias circuit 10, the output potential of the inverter INV2 in the bias circuit 65 rises and the transistor T8 in the bias circuit 65 is made conductive, so that the current I.sub.1 .mu.A flows from the node N4 to the node N3. The current flowing through the load transistors T9 and T10 when the power source voltage is Vcc' (which is higher than Vcc) are shown by one-dot-chain lines l.sub.2 and I.sub.4 in FIG. 2. As described previously, when the power source voltage Vcc rises to Vcc' by the noise on the power source, the current I.sub.1 .mu.A leaks from the nodes N2 and N4 through the transistors T8 in the bias circuit 10 and 65. As a result, the potential at the node N2 changes from V.sub.H to V.sub.1, and the potential at the node N4 changes from V.sub.R to V.sub.2 in FIG. 2. Therefore, during the noise generation on the power source, the potential at the node N2 becomes lower than the reference potential at the node N4 so that the output signal D* of the differential amplifier 30 changes from "0" level to "1" level. This level change of the output signal results in an erroneous data output.
FIG. 3 shows the potential changes with time at respective nodes upon generation of noises on the power source at time T.sub.1. The potential of the power source rises to Vcc' at a maximum because of the noise components during the period from time T.sub.1 to time T.sub.4. Therefore, the potential at the node N2 lowers from V.sub.H to V.sub.1, whereas the potential at the node N4 rises from V.sub.R to V.sub.2. The potentials at the node N2 is lower than that at the node N4 during the period from time T.sub.2 to time T.sub.3 so that the output D* of the current mirror type differential amplifier changes from "0" level to "1" level. During this period, erroneous data is outputted to the external circuit.
Another conventional EPROM is shown in FIG. 4. In this EPROM, the bias circuit 65 of the EPROM shown in FIG. 1 or FIG. 1A is replaced with a bias circuit 65A and the gate electrode of the reference cell RMC is supplied with a constant potential which is generated in a constant potential generating circuit 68.
The bias circuit 65A is obtained by replacing the load transistor T10 of the bias circuit 65 shown in FIG. 1 with a load transistor T10A having the same transistor size as that of the load transistor T9 of the bias circuit 10.
The constant potential generating circuit 68 has serially connected N-channel transistors T18, T19, T20, and T21. Of these transistors, only the transistor T18 is of a depletion type having a negative threshold voltage. The transistor T18 has the drain electrode connected to the power source, and gate and source electrodes connected to the drain and gate electrodes of the transistor T19. The gate electrode of the transistor T20 is connected to the source electrode of the transistor T19, and to the drain electrode of the transistor T20. The gate electrode of the transistor T21 is inputted with an inverted signal CE* of the chip control signal CE*, and the source electrode thereof is applied with the ground potential. The output terminal (node N68) of the constant potential generated circuit 68 is connected to the gate electrode of the reference cell RMC.
With the EPROM constructed as above, in order to set the level potential at the node N4 at the intermediate potential between the high level V.sub.H and low level V.sub.L at the node N2 of the bias circuit 10, the gate voltage of the reference cell RMC is set at a predetermined voltage below the power source voltage. The load current characteristics flowing through the load transistors T9 and T10A respectively of the bias circuits 10 and 65A are shown in FIG. 5. The load transistors T9 and T10A have the same transistor size so that they provide the same load current characteristics. It is assumed that the potential at the node N4 is the intermediate potential (V.sub.R) between the high level V.sub.H and low level V.sub.L at the node N2 when the current flowing through the reference cell RMC is a value Icell', as shown in FIG. 5. The reference cell current may be set at the value Icell' by adjusting the conducting resistance of the transistors T18, T19 and T20. It is therefore possible to set the potential at the node N4 at the intermediate potential V.sub.R between the high level V.sub.H and low level V.sub.L (refer to line l.sub.5). If the noise is generated on the power source and the current I.sub.1 .mu.A flows from the nodes N2 and N4 to the nodes N1 and N3 respectively, the potentials at the nodes N2 and N4 change to V.sub.1 and V.sub.2 as shown in FIG. 5 (refer to line l.sub.6). In this case, however, the output signal D* of the differential circuit will not change to "1" level because the potential V.sub.1 is higher than the potential V.sub.2. FIG. 6 shows the potential changes with time at respective nodes of the EPROM shown in FIG. 4. Although the potential of the power source changes during the period from time T.sub.1 to time T.sub.4, the potential at the node N2 will not become lower than the potential at the node N4. The EPROM therefore will not output any erroneous data.
The EPROM shown in FIG. 4 is however associated with a problem that the potential at the node N4 becomes higher than the intermediate potential between V.sub.H and V.sub.L as the potential power source becomes higher. The output potential of the constant potential generating circuit 68 shown in FIG. 4 depends only a little on power source voltage Vcc because the transistor T18 acts as the constant current means. As a result, the power source voltage dependency of the potential at the node N4 has the same inclination as that at the node N2 when a data-written memory cell is selected, as shown in FIG. 7.
Therefore, even if the reference potential is set at the intermediate potential between the high level V.sub.H and low level V.sub.L for the power source voltage of 5 V, the reference potential will become higher than the intermediate potential between the high level V.sub.H and low level V.sub.L if the power source voltage becomes higher than 5 V. In general, the higher the power source voltage becomes, the larger the noises which are generated on the power source line by the switching of an output buffer circuit. It is therefore desirable that the difference between the reference potential and the potential at the node N2 increases as the power source voltage rises. For this reason, the EPROM shown in FIG. 4 has a problem of less noise margin for a higher power source voltage.
Another example of the constant potential generating circuit 68 of FIG. 4 is shown in FIG. 8. The constant potential generating circuit shown in FIG. 8 is constructed of serial connected P-channel transistors T22 and T23, and depletion type N-channel transistor T24. The source electrode of the transistor T22 is connected to the power source, and the gate electrode thereof is applied with the chip control signal CE*. The gate electrode and drain electrode of the transistor T23 are connected together with the drain electrode of the transistor T24, and the potential at the interconnection node is sent as the output of the constant potential generating circuit to the gate electrode of the reference cell RMC. The gate and source electrodes of the transistor T24 are connected to the ground line. The size of the transistors T23 and T24 of the constant potential generating circuit is determined such that the potential at the node N4 becomes the intermediate potential between the high level V.sub.H and low level V.sub.L at the node N2 of the bias circuit 10.
In the EPROM wherein the constant potential generating circuit constructed as above, the potential of the gate electrode of the reference cell RMC becomes higher with a rise of the power source potential. As a result, the potential at the node N4 has the same inclination of the power source voltage dependency at the node N2 when a selected memory cell is in a data-erased state, as shown in FIG. 9. Therefore, even if the reference potential is set at the intermediate potential between the high level V.sub.H and low level V.sub.L for the power source voltage of 5 V, the reference voltage will become lower than the intermediate potential between the high level V.sub.H and low level V.sub.L if the power source voltage becomes higher than 5 V. Similar to the case of the EPROM shown in FIG. 4, there also arises the problem of less noise margin for a higher power source voltage.